1. Technical Field
This invention relates to test vector generation systems containing a data pattern generator. More particularly, it involves a test vector generation system that provides for the creation and generation of approximately all of the unique test vectors associated with the data pattern generator.
2. Discussion
Test vector generation systems are used in a wide variety of electronics and computer applications in order to provide for testing of computer and logic type systems. Testability is not, in general, concurrently compatible with tactical functionality. That is, if a test procedure is used on such a computer or logic system, the system must normally be placed in an inoperable state or taken out of its "normal functioning" mode. This causes this equipment to be of no use during this test interval. In order to limit this tactical dead time it generally becomes necessary to subject the computer or logic system to a less than complete test. Such testing minimizes the tactical downtime associated with the computer or logic system. However, automatic system fault isolation is often advantageous in order to minimize maintenance overhead and increase the readiness of the system. This is done by requiring a large and ideally exhaustive set of test vectors to be applied to the computer or logic system. Thus, it has become extremely important in some test applications to exhaustively test a computer or logic system. Such "dual" and "inopposite" objectives have been found to be very difficult to achieve.
Two prior approaches have generally been employed in this regard. Both of these approaches use a linear feedback type of shift register in order to generate a series of test vectors. The first approach begins the test vector generation using a default state. That is, this default state represents the state that the linear feedback shift register was in upon completion of the generation of the previous vector. This default state is used as the start initialization seed for generation of the next vector. The disadvantage of this approach is that it does not ensure that an exhaustive set of test vectors will be generated. For example, a 6 data bit long linear feedback shift register applying this technique to a 60 data bit long scan register chain, contained within an application interface unit, will typically only generate approximately 16 of the possible 64 unique test vectors. In general, the possible number of unique test vectors capable of being generated by a linear feedback shift register is approximately 2.sup.N where "N" is equal to the length of bits of data of the linear feedback shift register. Usually, one such data bit is assigned to every register within the linear feedback shift register.
The second approach to generating a series of test vectors is in generating these vectors by constantly resetting the linear feedback shift register to a reset state (i.e., to a state in which all of its registers contain logical O's). The linear feedback shift register is then cycled, or shifted one additional time than was previously done for the generation of the previous test vector. For example, if the scan register chain or application interface unit is of a length equal to 100, the first vector would be generated by cycling or shifting the linear feedback shift register approximately 100 times. The second vector would be generated by shifting 101 times after the linear feedback shift register is reset to its initial state. In general, test vector N is created and generated by having the linear feedback shift register shift a number of times equal to N+99. The disadvantage of this approach is that it introduces a latency penalty associated with shifting the correct start initialization seed into the linear feedback shift register prior to generating a test vector. In this particular example for instance, if one wished to do exhaustive testing using a 16 data bit long linear feedback shift register, the test would take approximately three hundred and twenty nine times as long as it would have taken if the aforementioned latency were not introduced. Clearly, improvements in both of these methods need to be made.